RTL设计与合成

Next Generation RTL Design for Advanced Nodes

RTL Synthesis

RTL建筑师is the latest addition to the digital design family of products.It is a predictive RTL design closure solution that provides early predictions of the impact RTL changes will have on implementability, power, performance, area and other quality metrics.

The Design Compiler family of products maximizes productivity with its complete solution for RTL synthesis and test.In the Design Compiler family of RTL synthesis products,设计编译器NXTextends the market-leading synthesis position of设计编译器图形.设计编译器NXT incorporates the latest synthesis innovations, delivering significantly faster runtimes, improved QoR, and extremely tight RC and timing correlation withIC Compiler II.设计编译器NXT uses advanced optimizations and shared technology with IC Compiler II place-and-route to deliver best-in-class quality-of-results at process nodes down to 5nm and beyond.

The Design Compiler family is also tightly linked to the SynopsysTestMAX family of test productsfor the fastest, most cost-effective path to high-quality manufacturing tests and working silicon;电力编译器, for low-power synthesis and optimization;Formalityfor equivalence checking;and theDesignWare库with its unequalled variety of synthesizable IP.

An important part of the design solution,Fusion Compileris the first RTL-to-GDSII solution enabling a highly-convergent, full-flow digital implementation.Fusion Compiler is built on a single, highly-scalable data-model and comprises common engines for timing, extraction, synthesis, placement, legalization, clock-topology-creation and routing.These best-in-class engines form a single, unified optimization framework that is the key enabler of Fusion Compiler’s full-flow convergence, leading QoR and enhanced time-to-results.