标准电池Libraries

As part of Synopsys’ foundation IP portfolio, the high-speed, high-density, and low-power DesignWare® Logic Libraries provide a complete standard cell platform solution for a wide variety of system-on-chip (SoC) designs.In addition to Synopsys' silicon-proven standard cell libraries, availablePower Optimization Kits (POKs)andEngineering Change Order (ECO) Kitsdeliver outstanding performance, with low power and small area in the advanced nodes ofleading foundries.

Ideal for tablet, smartphone, cell phone, graphics, networking, storage, and other high-performance applications requiring low power and high density, Synopsys' DesignWare Logic Libraries and内存编译器provide a unique set of options that enable SoC designers to optimize their products for speed, area, dynamic power, standby power, and cost.

Multiple Architectures, Multiple VTs, Multi-Channel Lengths

The standard cell libraries provide three separate architectures, high-speed (HS), high-density (HD), and ultra high-density (UHD), to optimize circuits for performance, power and area tradeoffs.

The standard cell libraries include multiple voltage threshold implants (VTs) at most processes from 180-nm to 65-nm and support multiple channel (MC) gate lengths to minimize leakage power at 40-nm and below.

SiWare Logic Libraries

设计Ware Embedded Memories and Logic Libraries are available for multiple foundries and process technologies, including GLOBALFOUNDRIES,SMIC, TSMC, andUMC.

设计Ware Duet Embedded Memories and Logic Libraries Datasheets

GLOBALFOUNDRIES 40LP-Duet Embedded Memories and Logic Libraries Datasheet
GLOBALFOUNDRIES 55LPe-Duet Embedded Memories and Logic Libraries Datasheet
SMIC 40LL-Duet Embedded Memories and Logic Libraries Datasheet
SMIC 65LL-Duet Embedded Memories and Logic Libraries Datasheet
台积电 16FF+ -Duet Embedded Memories and Logic Libraries Datasheet
台积电 16FFC-Duet Embedded Memories and Logic Libraries Datasheet
台积电 28HP-Duet Embedded Memories and Logic Libraries Datasheet
台积电 28HPC+ -Duet Embedded Memories and Logic Libraries Datasheet
台积电 28HPC-Duet Embedded Memories and Logic Libraries Datasheet
台积电 28HPM-Duet Embedded Memories and Logic Libraries Datasheet
台积电 40LP-Duet Embedded Memories and Logic Libraries Datasheet
台积电 65LP-Duet Embedded Memories and Logic Libraries Datasheet
UMC 28HLP-Duet Embedded Memories and Logic Libraries Datasheet
UMC 28HPC-Duet Embedded Memories and Logic Libraries Datasheet
UMC 40LP-Duet Embedded Memories and Logic Libraries Datasheet
UMC 40ULP - Duet Embedded Memories and Logic Libraries Datasheet

Highlights
Features
  • Maximum Performance
    • High-performance libraries for critical paths of GHz processors
    • Close timing in fewer iterations without sacrificing area or power
  • Minimum Power
    • Multi-channel libraries for 4X-5X static power reduction
    • Power Optimization Kits with over 200 cells
    • 支持 for low-power UPF and CPF EDA flows
  • Maximum Density
    • Patented NXT standard cell architectures for highest routing utilization
    • Multiple cell heights (# tracks) per process for optimal tradeoffs
    • Hand-crafted layout for maximum density
    • Deep cell set of functions and drive strengths for optimal cell choice
    • Optimal pin placement for highest routed density
  • High Yield
    • 设计-for-manufacturing (DFM)-aware design and validation
    • Redundant contacts
    • Electro-migration (EM)-compliant at highest speeds
  • Comprehensive Solution
    • Electrically, physically and EDA-view aligned with DesignWare Embedded Memory products
    • 多VDD与表征低电压,过载PVTS
  • Multiple Libraries per Process Node
    • 碱库包括在最小沟道长度多种架构/ VT的细胞组
    • 多通道长度库(MC),用于泄漏减少,在40纳米和更小的并减少管芯到管芯泄漏和定时的变化
    • 功耗优化套件使停机和多电压域
    • ECO套件仅启用金属后硅的修复成本,有效地解决的bug
    • 高性能芯(HPC)在40纳米及更小的数据通路与细胞和多位提供设计套件触发器
    • 灵活的,只有金属的设计变更在整个产品生命周期的金属可编程库
    • 超低漏电图书馆提供高达100X减少渗漏的建设始终保持接通块
  • Multiple Cell Architectures for Optimal Power, Performance, and Area
    • 高速(高)在关键路径的性能库为最终
    • 高密度(短)库与平衡PPA通用逻辑
    • 超高密度(最短)库最低功耗,最低成本和最高密度
  • Optimized Cell Sets
    • 丰富的综合型小区集中与多个细胞变异和驱动强度
    • 专业细胞如集成时钟gaters(ICG),多位触发器和路由支持细胞
  • Accurate Characterization
    • HSPICE®精度
    • 传播延迟和约束(建立,保持,拆卸和回收,最小脉冲宽度)
    • 在先进节点角具体提取
  • EDA Views
    • Liberty®时序,噪音和功耗,CCS时序,噪音和ECSM时机
    • 其他特种车型
  • Availability of Process, Voltage, and Temperature (PVT) Characterization Corners
    • 标准,过载和低电压PVT簇用于定时和泄漏
    • 用的DesignWare存储器编译器PVTS对准PVTS
    • 自定义PVT发展提供
  • Silicon proven using Split Lots at Advanced Nodes
    • 相关EDA模型
    • 低电压测试VDDMIN